1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of manufacturing the same and particularly to semiconductor devices having a marking recess for example for an alignment mark and methods of manufacturing the same.
2. Description of the Background Art
Conventionally, dynamic random access memories (DRAMs) and similar semiconductor devices have an alignment mark, a process management pattern and the like formed for photolithography. Such a mark, a pattern and the like are formed on a semiconductor substrate at a region other than an element formation region provided with a field effect transistor, a capacitor and other similar elements, i.e., an external region. FIGS. 22 and 23 are schematic cross sections for illustrating a method of conventionally manufacturing a semiconductor device, showing a step of loading a tungsten film into a contact hole of an element formation region, with an alignment mark or trench formed in an external region. With reference to FIGS. 22 and 23 a method of conventionally manufacturing a semiconductor device will now be described.
Initially, as shown in FIG. 22, in the element formation region on a semiconductor substrate (not shown) an interconnection 107 is formed and thereon an interlayer insulating film 101 is formed. In interlayer insulating film 101 a contact hole 103 is formed to reach interconnection 107. Furthermore, in an external region or a region other than the element formation region, interlayer insulating film 101 has a marking recess 102 serving as an alignment mark. Marking recess 102 has a width W2 of approximately 1 to 7 xcexcm, which is sufficiently greater than a width W1 of contact hole 103. Then, a barrier metal film 104 is provided to extend from an interior of contact hole 103 to an upper surface of interlayer insulating film 101. Barrier metal film 104 can be formed of a titanium nitride (TiN) film and a titanium (Ti) film provided in layers. Barrier metal film 104 is also provided simultaneously in marking recess 102 of the external region.
Then a tungsten film 105 having a thickness W3 is provided on barrier metal film 104 to fill contact hole 103. Since width W2 of marking recess 102 is much greater than width W1 of contact hole 103, marking recess 102 still has an opening reflecting the geometry of marking recess 102 even after tungsten film 105 is provided. That is, marking recess 102 would never be filled by tungsten film 105. If marking recess 102 serving as an alignment mark is filled with tungsten film 105 then it would not be employed as the alignment mark. As such, tungsten film 105 has a thickness set not to completely fill marking recess 102.
Then a chemical mechanical polishing (CMP) process is employed to remove tungsten film 105 and barrier metal film 104 located on the upper surface of interlayer insulating film 101, to provide a structure as shown in FIG. 23. As shown in the figure, the external region is provided with a pattern 108 for a region external to a chip, formed of marking recess 102, a barrier metal film 104a and a tungsten film 105a to serve as an alignment mark, and the element formation region is provided with a structure 109 therein formed of interconnection 107 and barrier metal and tungsten films 104b and 105b filling contact hole 103.
Then, a film deposition process for forming a structure such as an interconnection positioned on interlayer insulating film 101, a photolithography process employing marking recess 102 as an alignment mark, and other processes are performed to obtain a predetermined semiconductor device.
The above conventional method of manufacturing a semiconductor device, however, is disadvantageous, as described below:
When tungsten film 105 and barrier metal film 104 are chemically mechanically polished on the upper surface of interlayer insulating film 101 and thus removed therefrom, the slurry used in the CMP process is introduced into marking recess 102. Some of such slurry introduced into marking recess 102 can still remain therein even after it has undergone a washing step following the chemically mechanically polishing process. Consequently, as shown in FIG. 24, residual slurry 120 still exists in marking recess 102. Such residual slurry 120 causes a defect of a structure such as an interconnection formed in a subsequent step and hence a defect of the semiconductor device. Note that FIG. 24 is a schematic cross section for illustrating a disadvantage of a conventional semiconductor device.
Furthermore, with reference to FIG. 24, a conventional semiconductor device can have marking recess 102 having a bottom corner excessively etched and thus recessed to form a so-called subtrench 116. If such subtrench 116 is formed then in providing a structure in an overlying layer when the alignment mark corresponding to marking recess 102 is used to align a mask or the like the alignment mark""s position can be detected erroneously. Consequently, the structure formed in the overlying layer is offset from a predetermined position (or a structural defect occurs). Such a structural defect results in an operational defect of the semiconductor device and thus reduces the yield thereof.
FIGS. 25 and 26 are schematic cross sections for illustrating another disadvantage of a conventional semiconductor device. As shown in the figures, an external region is provided with a marking recess 119 serving as a pattern for a region external to a chip and having a greater width. As shown in the figures, the semiconductor device is basically similar in structure to the FIG. 23 semiconductor device except that marking recess 119 is greater in width than the FIG. 23 marking recess 102. In the FIGS. 25 and 26 semiconductor devices, marking recess 119 is used as a checking pattern further greater in width than an alignment mark, such as a film-thickness monitoring pattern.
With reference to FIG. 25, interlayer insulating film 101 is provided with marking recess 119 and contact hole 103 and then, as shown in FIG. 22, barrier metal film 104 (FIG. 22) and tungsten film 105 (FIG. 22) are provided. Then, barrier metal film 104 and tungsten film 105 are chemically mechanically polished on an upper surface of interlayer insulating film 101 and thus removed therefrom, when, with marking recess 119 having a large width, an abraser pad being used in the chemically mechanically polishing process contacts tungsten film 105 and barrier metal film 104 located on a bottom surface of marking recess 119 and as a result, as shown in FIG. 25, marking recess 119 would have a bottom portion with tungsten film 105a, barrier metal film 104a and interlayer insulating film 101 abrased and thus removed, as labeled 121.
Furthermore, as shown in FIG. 26, the chemically mechanically polishing process can result in marking recess 119 having an upper portion with tungsten film 105a and barrier metal film 104a abrased and thus removed, as labeled 122.
Marking recess 119 having its internal tungsten film 105a and barrier metal film 104 excessively removed can no longer be used as a film-thickness monitoring pattern. As a result, the film thickness cannot be controlled with high precision, also resulting in a reduction of the product yield.
The present invention contemplates a semiconductor device capable of preventing yield reduction and a method of manufacturing the same.
The present invention in one aspect provides a method of manufacturing a semiconductor device including an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, including the steps of: providing in the external region an interlayer insulating film having a marking recess; providing a covering film extending from an internal portion of the marking recess to an upper surface of the interlayer insulating film; providing a filling film located on the covering film and filling at least the marking recess; and chemically mechanically polishing and thus removing the covering film located on the upper surface of the interlayer insulating film, with the filling film filling at least the marking recess.
Thus the covering film can be chemically mechanically polished and thus removed from an upper surface of the interlayer insulating film after the marking recess is filled with a filling film. Thus the marking recess can be internally free from residue for example of slurry used in chemically mechanically polishing the covering film. Thus the semiconductor device can be free from a defect otherwise attributed to residual slurry. Thus a high yield of semiconductor devices can be achieved.
The filling film filling the marking recess before the chemically mechanically polishing (CMP) process is provided, can also prevent the process from damaging the covering film in the marking recess and a sidewall of the marking recess.
In the present method in one aspect the step of providing the filling film may include providing a resin film in the marking recess.
As such, following the CMP process the resin film serving as the filling film can be readily removed for example with an organic solvent.
In the present method in the above one aspect an organic resin film is preferably a resist film.
As such, a conventional resist application equipment such as a spin coater can also be used for applying the filling film to prevent a further hike of the cost of equipment for implementing the present invention.
In the present method in the above one aspect the step of providing the filling film may include filling the marking recess with a spin-on-glass film.
As such, liquid spin-on-glass (SOG) can be applied on a surface of the substrate and thus fill the marking recess and then thermally treated to ensure that the marking recess is filled with an SOG film. This in turn ensures that the marking recess is internally free for example from residual slurry.
In the present method in the above one aspect the step of providing the filling film may include filling the marking recess with an optically opaque film and in the present method in the above one aspect the step of removing the covering film may be followed by the step of partially removing the optically opaque film from an upper portion of the marking recess.
Herein the optically opaque film is a film opaque for an optical system for use in detecting the marking recess (for example for the light of a specific wavelength range for use in detecting an alignment mark corresponding to the marking recess) and it may be transparent for visible light. The opaque filling film can partially remain in the marking recess at a bottom thereof. As such, if the marking recess has a bottom portion having a subtrench or a similar structural defect, the opaque filling film existing at the recess""s bottom can prevent later detection of the structural defect. Thus, if the marking recess providing an alignment mark has a bottom portion including a structural defect, the structural defect can be prevented from contributing to erroneous detection of the position of the alignment mark.
In the present method in the above one aspect the optically opaque film is preferably a film formed through a spin-on-glass process and being mixed with a dopant to be opaque.
As such, a film that is optically opaque and fills the marking recess can be readily provided.
In the present method in the above one aspect the step of providing the filling film may include providing a phosphorus-containing, silicon oxide film in the marking recess.
As such, a facility conventionally used for providing a silicon oxide film can also be used to provide the filling film. Thus the present method can be implemented without preparing any additional facility. Thus the semiconductor device can be produced at a reduced cost.
Furthermore, the phosphorus-containing, silicon oxide film can be selectively removed for example through a vapor-phase HF reaction relative to an interlayer insulating film formed for example of silicon oxide film. This can facilitate removing only the filling film formed of the phosphorus-containing silicon oxide film after the CMP process is provided.
In the present method in the above one aspect the step of removing the covering film may be followed by the step of removing an upper surface layer of the interlayer insulating film to allow the covering film in the marking recess to have a portion protruding as seen from an upper surface of the interlayer insulating film.
Thus there can be readily obtained a semiconductor device including the marking recess having an upper portion covered with the covering film having a portion protruding as seen from an upper portion of the interlayer insulating film.
If the marking recess is used to provide an alignment mark and the recess underlies an opaque, overlying interlayer insulating film, a portion of the covering film protruding as seen from an upper surface of the interlayer insulating film can contribute to the formation of a protrusion on an upper surface of the overlying interlayer insulating film at the protruding portion of the covering film. This protrusion on the upper surface of the overlying interlayer insulating film can facilitate detection of the alignment mark. This can in turn reliably prevent erroneous detection of the alignment mark.
In the present method in the above one aspect the step of providing the interlayer insulating film preferably includes the steps of: providing an underlying interlayer insulating film in the external region; providing an overlying interlayer insulating film on the underlying interlayer insulating film; and partially removing the overlying and underlying interlayer insulating films to form the marking recess.
Forming the overlying interlayer insulating film of a material having an etching rate different than the filling film (i.e., a material hardly damaged by etching away and thus removing the filling film from the marking recess), ensures that the overlying interlayer insulating film is free from damage otherwise caused when the filling film is removed from the marking recess after the CMP process is provided. As a result, the covering film located on a sidewall surface of the marking recess can be prevented from having a protrusion, as seen from an upper surface of the interlayer insulating film, that would otherwise be attributed to the interlayer insulating film being partially removed when the filling film is removed.
In the present method in the above one aspect the step of providing the interlayer insulating film may include providing the interlayer insulating film extending to the element formation region. In the present method in the above one aspect the step of providing the covering film may be provided following the step of providing in the element formation region at the interlayer insulating film a recess smaller in width than the marking recess. Furthermore, the step of providing the covering film may include filling the recess with the covering film.
As such in a method of manufacturing a semiconductor device including the step of providing the element formation region with a recess such as a contact hole and providing a covering film to fill the recess the external region can have a marking recess internally completely free of residual slurry after the covering film is chemically mechanically polished and thus partially removed.
In the present method in the above one aspect the marking recess is preferably used to form at least one selected from the group consisting of an alignment mark and a process management pattern.
The alignment mark, the process management pattern and the like are greater in width than the contact hole formed in the element formation region. If in the interlayer insulating film provided for example with an alignment mark the element formation region is provided with a contact hole filled with a covering film corresponding to a conductor film, then the covering film is also introduced into the marking recess, although the covering film is only required to have a thickness sufficient to fill the contact hole and the covering film does not fill the marking recess for example for an alignment mark as the marking recess is greater in width than the contact hole. As such, in a region located over the marking recess the covering film would have an upper surface having a depression geometrically corresponding to the marking recess. As such, when the covering film is chemically mechanically polished and thus removed on an upper surface of the interlayer insulating film, slurry and the like conventionally remains in the marking recess (or in the depression). In contrast, the present invention, with a film filling the marking recess for example for an alignment mark, ensures that such residual slurry is prevented. Thus the present invention can be particularly significantly effective if it is applied to a method of manufacturing a semiconductor device including a marking recess for example for an alignment mark greater in width than an element such as a contact hole formed in an element formation region thereof.
The present invention in another aspect provides a semiconductor device manufactured in the method of manufacturing a semiconductor device, as described in the above one aspect.
This can prevent a reduction in the yield of semiconductor devices that is attributable for example to residual slurry in the marking recess.
The present invention in still another aspect provides a semiconductor device having an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, including: an interlayer insulating film provided in the external region and having a marking recess; and an optically opaque film arranged at a bottom of the marking recess.
As such, if an alignment mark provided by the marking recess is to be detected and the marking recess has a bottom portion having a structural defect such as a subtrench, the opaque film existing at the recess""s bottom can prevent detection of the structural defect. This can in turn prevent the erroneous detection of the position of the alignment mark that is otherwise attributable to such a structure defect.
The present invention in still another aspect provides a semiconductor device having an element formation region provided on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, including: an interlayer insulating film located in the external region, having an upper surface and provided with a marking recess having a sidewall; and a covering film provided on the sidewall of the marking recess and partially protruding as seen from the upper surface of the interlayer insulating film.
If in the semiconductor device the marking recess is used to provide an alignment mark and the alignment mark underlies an opaque, overlying interlayer insulating film, a portion of the covering film protruding as seen from an upper surface of the interlayer insulating film can contribute to the formation of a protrusion on an upper surface of the overlying interlayer insulating film at the protruding portion of the covering film. The protrusion on the upper surface of the overlying interlayer insulating film can facilitate detection of the alignment mark. This can in turn reliably prevent erroneous detection of the alignment mark. Thus the semiconductor device can be free from a structural defect attributable to erroneous detection of the alignment mark. Thus yield reduction otherwise attributed to such a structural defect can be prevented.
The present invention in still another aspect provides a semiconductor device having an element formation region arranged on a semiconductor substrate and an external region arranged on the semiconductor substrate and surrounding the element formation region, wherein the external region has a marking recess having a sidewall. The external region also has an underlying interlayer insulating film and an overlying interlayer insulating film overlying the underlying interlayer insulating film. The sidewall of the marking recess includes a surface of the underlying interlayer insulating film and a surface of the overlying interlayer insulating film. Furthermore the semiconductor device in the above, still another aspect includes a covering film provided on the sidewall of the marking recess.
Preferably, the overlying interlayer insulating film is formed of a material having an etching rate different than the filling film (i.e., a material hardly damaged while the filling film is etched away and thus removed from the marking recess). This can reliably prevent the overlying interlayer insulating film from being damaged in the present method of manufacturing a semiconductor device when the filling film is removed from the marking recess after the CMP process is conducted with the marking recess having the filling film therein. As a result, the covering film on a sidewall of the marking recess can be free of a protrusion on an upper surface of the overlying interlayer insulating film that is attributable to the overlying interlayer insulating film being partially removed when the filling film is removed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.